Regarding an integration density of an integrated circuit, Moore's law has been well known. Moore's law describes that an integration density doubles approximately every year. This Moore's law has been supported by development in a semiconductor micro processing technique. However, since the micro processing technique has reached a nano level, it is difficult to develop the micro processing technique at the same pace as it has been. For this reason, it has been said that Moore's law will reach its limit in the next generation or the generation after. As it is difficult to develop the micro processing technique, attention is drawn to a three-dimensional integrated circuit.
As depicted in FIG. 1A, a conventional system LSI1 is a two-dimensional integrated circuit in which functional blocks 3 such as a micro processer, a logic circuit, various memories, an input/output interface circuit or a communication controlling circuit is placed on a single chip 2. In comparison, as depicted in FIG. 1B, in a three-dimensional integrated circuit 4, the functional blocks 3 of the system LSI1 are divided and stacked in a three-dimensional manner. When the functional blocks 3 are stacked, a chip 5 of each layer has a thickness in the range of, for example, several μm to several hundreds μm. This three-dimensional integrated circuit has various advantages capable of reducing a length of a wiring, capable of densifying components, capable of increasing a signal processing rate, and capable of reducing power consumption. The three-dimensional integrated circuit has already been applied to a CMOS image sensor and will be applied to an integrated circuit such as a NAND, a DRAM or a logic circuit.
As a technique for implementing a three-dimensional integrated circuit, a method of alternately repeating a FEOL (Front End Of Line) process and a BEOL (Back End Of Line) process on a wafer, a method of stacking a chip on another chip (hereinafter, referred to as “Chip on Chip method”), a method of attaching and stacking wafers (hereinafter, referred to as “Wafer on Wafer method”), and a method of stacking multiple chips on a wafer (hereinafter, referred to as “Chip on Wafer method”) have been known.
In the method of alternately repeating the FEOL process and the BEOL process, the FEOL process in which components such as a transistor are formed on a wafer and the BEOL process in which the formed components are connected to each other by wiring are repeated alternately. By repeating these processes, a three-dimensional integrated circuit can be formed on the wafer. However, there is a procedural problem in this method. That is, it is difficult to perform the FEOL process after the BEOL process. Further, if a defect arises in any one of the repeated FEOL process and BEOL process, the whole product becomes defective, resulting in a decrease in production yield.
In the Chip on Chip method, a chip cut from a wafer is stacked onto another chip without using a wafer. Only a high-quality chip called as “KGD (Known Good Die)” can be stacked, and, thus, production yield can be increased. The KGD refers to a die (i.e. chip) whose characteristics and reliability are verified. However, since this method is performed in a chip-level, there is a problem that a manufacturing throughput is greatly decreased.
In the Wafer on Wafer method, wafers having thereon components are stacked in a wafer-level. That is, a process can be performed in a wafer size level, and, thus, a throughput can be increased. However, since the wafer may include a defective chip (a chip yield from a wafer is not 100%), if the wafers are getting stacked more, a probability of producing defective products becomes higher. As a result, a production yield is decreased.
In the Chip on Wafer method, a chip is placed on a wafer and another chip is stacked onto the chip on the wafer. Finally, numerous three-dimensional integrated circuits are formed on the wafer. In the same manner as the Chip on Chip method, only a high-quality chip can be stacked, and, thus, a production yield can be increased. Further, it is possible to increase a throughput by using a wafer as compared with the Chip on Chip method. However, it requires that a robot picks thousands of chips one by one and positions each chip on the wafer. Therefore, the throughput is not much increased. Further, when each chip is mechanically positioned, the positioning accuracy is about 1 μm at most, and, thus, the positioning accuracy cannot be increased further.
In order to solve the problem of the Chip on Wafer method, the present inventors have suggested a method of manufacturing a three-dimensional integrated circuit for positioning a chip on a supporting substrate by using a self-organizing function (see Patent Document 1). In this manufacturing method of a three-dimensional integrated circuit, numerous chips are automatically positioned on a transcription substrate by using surface tension of water. Further, the transcription substrate to which the numerous chips are temporarily attached is reversed, and the numerous chips are collectively transferred from the transcription substrate to the supporting substrate.
To be specific, as depicted in FIG. 2, a water film 8 inflated in a convex shape by the surface tension is formed on a rear surface of a chip 6 (S1). Further, the water film 8 inflated in a convex shape by the surface tension is also formed at a temporary attachment area 7a of a transcription substrate 7 (S1). Subsequently, the chip 6 is mounted on the temporary attachment area 7a of the transcription substrate 7 with a rough positioning accuracy by using a chip bonder (S2). Then, the chip 6 is automatically positioned on the temporary attachment area 7a of the transcription substrate 7 by the surface tension of water (S3). Thereafter, the chip 6 is pressed onto the transcription substrate 7 by using a pressing plate 9. Thus, water exists at a minute gap between the chip 6 and the transcription substrate 7 and, at the same time, unnecessary water is removed (S4). The chip 6 is temporarily attached to the transcription substrate 7 by attracting force of the water existing at the gap between the chip 6 and the transcription substrate 7. Subsequently, the transcription substrate 7 to which numerous chips 6 are temporarily attached is reversed (S5). At this time, the chip 6 is temporarily attached to the transcription substrate 7 by the attracting force of water. Then, the transcription substrate 7 is moved toward a supporting substrate 10 and the chip 6 is finally attached to the supporting substrate 10 (S6). When the chip 6 is finally attached to the supporting substrate 10, the water between the chip 6 and the transcription substrate 7 is vaporized by heating the chip 6. Accordingly, the numerous chips 6 are detached from the transcription substrate 7 (S7). As described above, the chips 6 temporarily attached to the transcription substrate 7 can be transferred and finally attached to the supporting substrate 10.
Patent Document 1: PCT Publication No. WO2006/77739 (see paragraphs [0149] to [0164])